Friday, July 1, 2011

DBF Technique in Bistatic Radar and Its VLSI Array Processing Implementation

Student: Hang Li
Supervising Professor: Yaohuan Gong
The University of Electronic Science and Technology of China
Chengdu, Sichuan, P.R. China
March 1993


In this thesis, engineering realization of adaptive Digital Beam Forming in practical Bistatic Radar has been discussed. Bistatic radar has excellent advantages against ECM in modern electronic war and DBF is the crucial technique. For this purpose, rapid convergence adaptive signal processing algorithms and their VLSI array processing implementation become the major topics.
Givens rotation QRD and G-S orthogonalization methods were used as computation core of adaptive algorithm here due to their stability, fast convergence and regular nature of computation. Least Square criterion has been adopted to derive optimum weight computation for adaptive DBF, and a iterative algebraic model suitable for array processing implementation resulted. The derived algorithm has been shown to be mathematically equivalent to SMI algorithm. Thus, established statistical analysis of SMI can be borrowed in evaluation QRD and GS.
For implementation with VLSI, variant algorithms were derived such as square root and division free algorithms of QRD and GS, among them, CORDIC has been emphasized. In addition, efficient VLSI array structures and mapping procedure were established. This enable array processing algorithms of different size to be implemented on the same array processor. As a generalization of the above results array modules of basic matrix computation have been established. More complicated matrix related algorithms can be mapped into array processor simply by reconfiguration of these elementary computing units. For the first time, I put forward a bi-directional systolic array which has a high performance-cost ratio.
Necessary computer simulations and their results have been presented. They include comparison of nulling performance, convergence rate of different algorithms, and the efficiency of different array structure. Besides, related hardware and software experiments were described. Here, a linear array processor of 4 TMS320C25s have benn constructed by the author to implement the QRD. The results of this thesis have be applied successfully to the practical DBF radar in 38th research institute of China's Department of Electronic Industry.

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